As a typical representative of the third generation of wide bandgap semiconductor materials, SiC has the characteristics of high critical breakdown field strength, high thermal conductivity, high electron saturation drift velocity, large bandgap width, and strong radiation resistance. It can meet the requirements of the next generation of power electronic equipment for power devices to work under harsh conditions such as higher power, smaller volume, and high temperature and high radiation. It has the advantages of reducing size, reducing power loss, and reducing cooling requirements. Silicon carbide has become an indispensable material for high-end applications in power electronics, and has brought revolutionary changes in new energy vehicles, photovoltaics, energy storage, rail transportation, smart grids and other fields. In the past few years, the popularity of electric vehicles has driven the continuous supply and demand of SiC power devices. At present, SiC power devices are mainly produced by 6-inch diameter wafers. The factory standards of 6-inch epitaxial wafers of mainstream epitaxial manufacturers are: thickness non-uniformity is not more than 3%, doping non-uniformity is not more than 6%, and triangle and drop defect density is not more than 0.5cm-2.。 

Leading companies in the SiC industry have been researching and developing 8-inch SiC wafers. Cree (now renamed Wolfspeed) and II-VI Incorporated (now renamed Coherent) demonstrated 8-inch SiC wafers in 2015. In 2022, Wolfspeed opened the world's first integrated 8-inch SiC chip factory. In Europe, the European SiC 8-inch pilot production line project REACTION (euRopEAn siC eighT Inches pilOt-liNe), composed of 27 partners from industry and academia, developed an 8-inch SiC pilot production line for the production of power devices in 2022. The project adopted a step-by-step development strategy to promote 8-inch SiC wafers. Low-quality mechanical-grade wafers are used to support the development of production line equipment compatible with 8-inch wafer sizes, test and optimize the processing capabilities of different production tools in the production line; high-quality process-grade wafers are used to grow epitaxial films, develop and optimize epitaxial process parameters, and ultimately produce power devices. The project carried out epitaxial growth on a horizontal commercial 8-inch machine developed by LPE. The indicators of the grown epitaxial film are as follows: thickness non-uniformity is 2.1%, and concentration non-uniformity is 3.3%. It can be seen that the non-uniformity of the epitaxial film has reached the commercially available level, which is a good progress. However, the defect rate is as high as 3.05 cm-2, of which the killer defect density is as high as 1.35 cm-2, which cannot meet the needs of back-end chip commercial mass production.

In the development of domestic 8-inch SiC wafers, from 2021 to the end of 2023, more than 10 companies and research institutions including Shandong University, Beijing Tianke Heda Semiconductor Co., Ltd. (referred to as "Tianke Heda"), Shanxi Shuoke Crystal Co., Ltd. (referred to as "Shanxi Shuoke"), and Guangzhou Nansha Wafer Semiconductor Technology Co., Ltd. (referred to as "Nansha Wafer") have successively released 8-inch conductive 4H-SiC substrate wafers, and also conducted a partition simulation study on the thermal field of the 8-inch crystal growth furnace. From the comparison in Table 1, it can be seen that although the research and development time is relatively late compared to foreign countries, the number and speed of domestic companies in the research and development of 8-inch wafers are rapidly catching up with foreign countries.

The 8-inch epitaxy link of SiC is also developing rapidly in China. Xiamen University released the results of 8-inch 4H-SiC epitaxy in March 2023. The thickness and doping concentration non-uniformity are 2.3% and <7.5% respectively, and the surface defect density is <0.5 cm-2. It can also be seen from the data in Table 2 (as of January 1, 2024) that the 8-inch SiC epitaxy link in China is also developing rapidly.

Nansha Wafer has delivered multiple batches of 8-inch substrates to Guangdong Tianyu. The substrates were characterized from the perspective of surface morphology and electrical properties. The average thickness of the delivered wafers measured by FlatMaster 200 was 500.8 μm, indicating that the slicing process provided good wafer-to-wafer repeatability; the average value of the total thickness variance (TTV) within the wafer was about 2.4 μm; the average warpage of the delivered wafers was 7.1 μm, which can meet the basic requirements of subsequent production equipment. The wafer resistivity measured by the non-contact atlas system LEI 1510 showed an average value of 22.8 mΩ∙cm for the delivered wafers, and the intra-wafer deviation was less than 3% within the target range of 15~25 mΩ∙cm. Wet etching is a fast and effective method for measuring the distribution of dislocation defects in substrates and is widely used in the industry. The Nansha Wafer Research Team used molten KOH to selectively etch the prepared 8-inch conductive 4H-SiC single crystal substrate, with an etching temperature of 450 ℃ and an etching time of 40~50 min. Due to the anisotropy of the corrosion rate, regular-shaped corrosion pits will form at the defect position. The etching rate of threading screw dislocation (TSD) is higher than that of threading edge dislocation (TED), making the corrosion pits of TSD larger than TED, so the two can be easily distinguished based on the microscope image. Mixed screw dislocation (TMD) is counted as TSD, while base plane dislocation (BPD) is a typical shell shape that can be easily identified and calculated. Under appropriate corrosion conditions, the dislocation defect corrosion pits on the Si surface of the SiC wafer are clear in shape, moderate in size, fully exposed and without overlap. The etched wafers were repeatedly cleaned with boiling alcohol and distilled water, and tested after being wiped dry. The dislocation defect detector (model LFMSiC) is used to automatically identify and count the number of characteristic corrosion pits corresponding to different types of dislocations. The equipment can accurately identify various types of dislocations, and the results of the visual recognition system are manually reviewed and confirmed to ensure the reliability of the results of the current method, thereby obtaining the TSD and BPD density and distribution of the 8-inch 4H-SiC substrate wafer. As shown in Figure 3, the average BPD density is 251cm-2, and the average TSD density is less than 1cm-2. The preparation of 8-inch conductive 4H-SiC single crystal substrate wafers with near "zero TSD" and low BPD density is achieved.   

In this study, epitaxial growth at a rate of 68.66 μm/h was achieved on an 8-inch wafer, and an epitaxial layer with a nominal thickness of 11.44 μm and a doping concentration of 10.50×1015 cm-3 was obtained. The thickness of the epitaxial layer was measured by infrared fast Fourier transform spectroscopy (FT-IR), the doping concentration was measured by mercury probe method, the surface roughness of the epitaxial film was detected by atomic force microscopy (AFM), and the surface defects were observed by Sica88 surface inspection system. Figures 4 and 5 show the radial distribution of the thickness and doping concentration of the epitaxial layer grown on an 8-inch SiC wafer, respectively. The average thickness of the epitaxial layer is 11.44 μm, the standard deviation is 0.10 μm, and the thickness non-uniformity evaluated by the ratio of standard deviation to average value is 0.89%. The average doping concentration of the epitaxial layer is 10.50×1015cm-3, the standard deviation is 0.22×1015cm-3, the doping non-uniformity is 2.05%, and the AFM characterization results show that the surface root mean square roughness is 0.162 nm, and the triangle + drop defect density is 0.11 cm-2. Compared with the factory standard of epitaxial wafers, it can be found that the non-uniformity and killer defect density of this experimental result are better than the 8-inch epitaxial wafer data published in Table 2, and also reach the level of 6-inch excellent epitaxial wafers, which fully meets the indicators required for mass shipments.

Achieving high-quality 8-inch SiC wafer manufacturing and epitaxial growth is a fundamental step in promoting the production of next-generation large-size power devices. This article outlines the establishment and progress of the 8-inch SiC wafer industrial test line under the coordination of Guangdong Tianyu. The ingot was grown by expanding the diameter using a new PVD crystal growth furnace, and the 8-inch SiC substrate wafer was obtained after cutting, grinding and polishing. The measurement results show that the average BPD density of the 8-inch SiC substrate wafer is as low as 251 cm-2, and the average TSD density is less than 1 cm-2, achieving an 8-inch substrate with near "zero TSD" and low BPD density, which can meet the requirements of epitaxy and chip processing production. Using vertical SiC domestic epitaxial equipment, epitaxial growth was carried out on domestic 8-inch wafers developed by Nansha Wafer Company in Tianyu Semiconductor Laboratory, achieving a rapid epitaxial growth rate of 68.66 μm/h, a thickness non-uniformity of 0.89%, and a doping non-uniformity of 2.05%. These two indicators and defect density have reached the excellent level of 6-inch epitaxial film, which can fully meet production needs. Compared with the results published abroad, the thickness and doping uniformity are better than the foreign data, while the defect density is only 1/4 of the foreign data. The results of the repeatability test found that the 8-inch epitaxy in this study has good repeatability and good stability, and can be used for large-scale trial production and further mass production research and optimization. The chip production line production tools were tested and improved using 8-inch wafers to achieve 8-inch compatibility. This research work has taken an important step in promoting large-scale chip manufacturing of 8-inch SiC wafers. This study proves that the localization of equipment and materials in the entire SiC industry chain has made great achievements. After several years of catching up with the 6-inch industrialization, domestic companies have caught up in the 8-inch SiC industrialization, and have done better than foreign countries in wafer preparation and epitaxy.

The core goal of the SiC industry's transition to 8-inch wafers is to reduce costs and expand applications. At present, the research on 8-inch SiC wafer preparation and epitaxial application has solved the problem of going from scratch. Looking forward to future research directions, the next step will focus on continued optimization to improve efficiency and reduce costs in mass production. At the same time, it is necessary to continue 8-inch batch testing and mass production in subsequent chip manufacturing links to discover improvements in materials and equipment, further improve stability and reduce defect rates, study equipment repeatability, continue process optimization, promote the rapid industrialization and localization of 8-inch SiC epitaxy, and promote the entire industry to leap to large sizes.